As use of computer systems becomes more pervasive, there is a growing need to limit energy consumption of computers. Computer energy consumption impacts the design and usage models of computer systems of any kind, such as mobile devices, hand-held PDAs, laptops or also farms of computer clusters and data centers.
As well known, energy is directly proportional to power consumption. Power consumption can be limited for example by a budget of energy, either imposed by the power station, by a real budget for electric energy/power or even by the battery life in case of mobile and wireless computing. Power consumption is characterized by average power and peak power. The average power affects energy consumption and is dependent to a great extent on the workload a machine is executing, while peak power has a very important effect on power delivery network design and reliability. When peak power occurs to be beyond a certain limit in an integrated chip (IC), the power delivery network associated with it fails, thereby causing permanent damages. Such power delivery network failure is mainly due to high current density causing electro-migration in the metal lines, which in turn causes a power spiral resulting in the breaking of metal lines and in functional failure.
The ICs in a computer system have the highest power consumption among the different computer components, and are accordingly more likely to crush. Microprocessors are the largest computer ICs and comprise a high density of transistors on a single chip for facilitating high level of integration of multiple core and hardware threads, which makes achieving low power designs particularly challenging. This is the main cause of the high power consumption of the highly dense multi-core/multi-threaded microprocessors. There is accordingly a need to manage microprocessors' high activities to save energy and/or increase reliability and in particular job scheduling activities which facilitates a high level of utilization of the multi-core/multi-threaded hardware structures, through simultaneously running of many software threads.
One known approach to this problem is the one taken in US2006/107,262. US 2006/107,262 provides a thread scheduling technique for multi-core systems relying on the compiler to classify the threads as complex/high power or simple/low power, then schedule threads to run on the different cores by distributing the threads on the cores in a way that reduces the power/thermal density. However, US2006/107,262 is not adapted to multi-threaded processors in which more than one thread runs on each core. Further, US20060107262 considers that a thread has a fixed power consumption behaviour over its life cycle, so that the compiler can classify the thread to either high or low power, and thereby does not take into account the variation of the power consumption of each thread during its execution.
There is accordingly a need for a job scheduling method and system in a multi-core/multi-threaded processor that lowers peak power and average power levels.